When the channel length of a metal oxide semiconductor field effect transistor (MOSFET) becomes smaller continuously, many negligible effects in the long-channel model of the MOSFET becomes more significant, and has even been a dominant factor determining its properties. These effects are commonly referred to as short channel effects. The short channel effect deteriorates electrical properties of the device, which, for example, leads to a reduced gate threshold voltage, increased power consumption, and a lowered signal-to-noise ratio.
To suppress the short channel effect, the channel has to be doped with more elements such as phosphorus, boron, and the like, which, however, decreases the carrier mobility in the channel of the device. Moreover, it is difficult to provide a steep doping profile in the channel, which in turn leads to a severe short channel effect. Furthermore, conventional strained silicon technology in SiGe PMOS encounters a bottleneck and may not apply larger stress to the channel. Furthermore, there also exists a bottleneck for the thickness of the gate oxide dielectric layer, and thinning of the gate oxide may not follow the decreasing of the gate length. Consequently, the gate dielectric layer has larger leakage. With continuous decrease of the feature size, the resistance for the source/drain regions will increase and the power consumption of the device will become larger.
At present, the main idea in the industry is to improve conventional planar device technology by decreasing thickness of the channel region and eliminating the neutral layer below the depletion layer in the channel so that the depletion layer in the channel occupies the whole channel region, which is referred to as a fully depleted device. As a comparison, the conventional planar device is a partially-depleted device.
However, it is required that the silicon layer in the channel have an extremely small thickness for a fully depleted device. The conventional manufacturing process, especially the conventional manufacturing process on the basis of bulk silicon, is difficult to provide a semiconductor structure as required, or has a high manufacturing cost. Even for an emerging SOI (silicon-on-insulator) process, it is still difficult for a silicon layer in the channel to have a small thickness. With respect to the implementation of a fully depleted device, researches are focused on three-dimensional device designing, i.e. fully depleted double-gate or three-gate technology.
The three-dimensional device, which is also referred to as a vertical device, is a device in which cross sections of source/drain regions and a gate are not located in the same plane, which is substantially a FinFET (fin-type field effect transistor).
In the three-dimensional device, the source/drain regions are independent parts which are not included in bulk silicon or in a SOI layer. Thus, a fully depleted channel having an extremely small thickness can be made by etching.
One proposed three-dimensional semiconductor device is shown in FIG. 33, which comprises a semiconductor substrate 20 on an insulating layer 10, source/drain regions 30 adjacent to two opposite first sidewalls 22 of the semiconductor substrate 20, a gate 40 on second sidewalls 24 adjacent to the first sidewalls 22 of the semiconductor substrate 20. A gate dielectric layer and a work function metal layer, which are sandwiched between the gate 40 and the semiconductor substrate 20, are not shown in the figure. In the semiconductor device, edge portions of the source/drain regions 30 may be extended so that the width of the source/drain regions 30 in a direction indicated by xx′ is larger than the thickness of the semiconductor substrate 20, so as to decrease resistance of the source/drain regions. However, when the width d of the source/drain regions 30 increases, the parasitic capacitance between the source/drain regions 30 and both the gate 40 and the semiconductor substrate 20 will also increase. Consequently, RC (resistance-capacitance) delay increases, or AC (alternating current) characteristic deteriorates.